1. Field of the Invention
The present invention relates to a transmitting apparatus for outputting a signal of binary levels over a communication line or the like.
2. Description of the Background Art
In Japanese Patent Laid-open No. Hei 5-292101, there is proposed a communication apparatus in which signals are exchanged among a plurality of communication units through a communication line. Each communication unit includes a transmitting circuit for alternately generating a high level signal or a low-level signal and for outputting the generated signal to the communication line. Each communication unit further includes a transmission control circuit for inputting a control signal to the transmitting circuit so that the transmitting circuit outputs the high-level signal or the low-level signal.
In Japanese Patent Laid-open No. Hei 5-292101, the communication apparatus is adapted to reduce the effect of stray capacitance between the communication line and ground which slows down communication, and hence to improve communication speed. The transmitting circuit includes a timing circuit for outputting a timing signal for a predetermined period of time after inversion of the level of the control signal from a first level to a second level, a first transistor responsive to the timing signal for outputting either of the high level signal and the low level signal, and a second transistor responsive to the inversion of the level of the control signal from the second level to the first level for outputting a signal at the other level to the communication line.
A further conventional type of transmitting apparatus is the so-called totem pole type in which a first transistor for outputting a high-level signal to a communication line and a second transistor for outputting a low-level signal to the communication line are connected in series and interposed between power source terminals. FIG. 6 is a circuit configuration diagram showing an example of a conventional totem pole type transmitting apparatus.
FIG. 6 illustrates transmitting apparatus 101 including a non-inverting signal output terminal 103 for outputting a signal having a same logical level as the logical level of transmitted data supplied to the data input terminal 102 and an inverting signal output terminal 104 for outputting a signal having a logical level obtained by reversing the logical level of the transmitted data supplied to the data input terminal 102. Transmitting apparatus 101 further includes an invertor (logically inverting circuit) 105 for inverting the logical level of the transmitted data supplied to the data input terminal 102 and two output circuits 106 and 107.
Output circuit 106 includes a PNP transistor Q1, an NPN transistor Q2, a P-channel enhancement field effect transistor Q3, an N-channel enhancement field effect transistor Q4, and the corresponding peripheral circuits for each of the respective transistors. The emitter of PNP transistor Q1 is connected to a positive power source V+ and the collector of PNP transistor Q1 is connected to the non-inverting output terminal 103. The base of PNP transistor Q1 is connected to the output terminal of invertor 105 through base resistor R1. The emitter of NPN transistor Q2 is connected to ground (or a negative power source) and the collector of NPN transistor Q2 is connected to non-inverting output terminal 103. The base of NPN transistor Q2 is connected to the output terminal of invertor 105 through base resistor R3. Non-inverting output terminal 103 is connected to positive power source V+ through pull-up resistor R5. When PNP transistor Q1 and NPN transistor Q2 are both in an OFF state (idle state), the logical level of non-inverting output terminal 103 is held at a HIGH level by means of pull-up resistor R5.
Output circuit 107 is substantially the same as output circuit 106 described above except that output terminal 104 is connected to ground through resistor R10. Also, there is no invertor inserted between the base inputs of transistors Q5 and Q6 and data input terminal 102 in output circuit 107. Operation of transmitting apparatus 101 will be described as follows.
Output circuit 106 is adapted such that the base currents of PNP transistor Q1 and NPN transistor Q2 are controlled in accordance with the output of invertor 105 such that either of transistors Q1 and Q2 are turned on based on the output of invertor 105. When the logical level of transmitted data supplied to data input terminal 102 is HIGH, the output of invertor 105 is brought to a LOW level. When the output of invertor 105 is LOW, no base current is supplied to NPN transistor Q2 and NPN transistor Q2 is thus brought to an OFF state. Meanwhile, since a base current is not supplied to PNP transistor Q1 through base resistor R1 in this case, PNP transistor Q1 is maintained in an ON state. Thereby, the output of the non-inverting output terminal 103 is brought to a HIGH level.
When the logical level of the transmitted data supplied to data input terminal 102 is LOW, the output of the invertor 105 is brought to a HIGH level. When the output of invertor 105 is HIGH, a base current is supplied to NPN transistor Q2 through base resistor R3 and NPN transistor Q2 is brought to an ON state. At the same time, PNP transistor Q1 is brought to an OFF state. Thereby, the output of non-inverting output terminal 103 is brought to a LOW level.
In bipolar transistors such as PNP transistors and NPN transistors, even when the supply of base current is cut off, a time delay is produced until the collector current is cut off by the effect of electric charge stored in the base region and the like. In order to shorten the cut-off delay time (turnoff time), conventional transmitting apparatus 101 includes a field effect transistor between the base and the emitter of each transistor. By turning the field effect transistor on to short-circuit the base with the emitter through a low impedance, charge on the base is forcibly discharged. By forcibly discharging the charge stored on the base, cut-off delay time (turn off time) can be shortened. This operation will be described as follows.
When the logical level of the transmitted data supplied to data input terminal 102 is HIGH, then P-channel enhancement field effect transistor Q3 is in an OFF state and PNP transistor Q1 is brought to an ON state by the LOW level output of invertor 105. When the logical level of the transmitted data supplied to data input terminal 102 is changed from HIGH level to LOW level, P-channel enhancement field effect transistor Q3 is brought to an ON state. By turning on P-channel enhancement field effect transistor Q3, the charge stored on the base of PNP transistor Q1 is forcibly discharged. Thereby, the cut-off delay time (turn off time) of PNP transistor Q1 is shortened.
On the other hand, when the logical level of the transmitted data supplied to data input terminal 102 is LOW, N-channel enhancement field effect transistor Q4 is in an OFF state and NPN transistor Q2 is brought to an ON state by the HIGH level output of invertor 105. When the logical level of the transmitted data supplied to data input terminal 102 is changed from LOW level to HIGH level, N-channel enhancement field effect transistor Q4 is brought to an ON state. By turning on N-channel enhancement field effect transistor Q4, the charge stored on the base of NPN transistor Q2 is forcibly discharged. Thereby, the cut-off delay time (turn off time) of NPN transistor Q2 is shortened.
Since conventional transmitting apparatus 101 of FIG. 6 employs field effect transistors for shortening the cut-off delay time (turn off time) of the bipolar transistors, the number of discrete components constituting each of output circuits 106 and 107 is increased. It is therefore considered advantageous to provide circuits for shortening cut-off delay time (turn off time) of bipolar transistors as in the form of an integrated circuit (IC) by employing three-status buffers as will be described as follows.
FIG. 7 is a circuit configuration diagram of a transmitting apparatus adapted to shorten cut-off delay time (turn off time) of bipolar transistors by the use of three-status buffers. The transmitting apparatus 111 shown in FIG. 7 includes a logical circuit portion 112 and output circuits 113 and 114. The logical circuit portion 112 can be provided in the form of an IC with the logical circuit portions put together. Each of output circuits 113 and 114 are realized by eliminating the field effect transistors from each of output circuits 106 and 107 of FIG. 6. Otherwise, the circuit configuration of output circuits 113 and 114 are the same as the circuit configurations of output circuits 106 and 107 of FIG. 6.
Logical circuit portion 112 includes an invertor 105 and four three-status buffers G1-G4. The input terminal G1a of first three-status buffer G1 is connected to the output terminal of invertor 105. The output terminal G1b of first three-status buffer G1 is connected to the base of PNP transistor Q1. The output enable terminal G1c of first three-status buffer G1 is connected to the output terminal of invertor 105.
First three-status buffer G1, when the logical level of the output enable signal supplied to output enable terminal G1c is LOW, brings output terminal G1b to a high-impedance state. When the logical level of the output enable signal supplied to output enable terminal G1c is HIGH, first three-status buffer G1 outputs a signal at the same logical level as the logical level of the input signal supplied to input terminal G1a. The output impedance of first three-status buffer G1 is sufficiently smaller than the resistance value of base-emitter resistor R2 of PNP transistor Q1. Operation of the first three-status buffer G1 will be briefly described as follows.
When the logical level of the transmitted data supplied to data input terminal 102 is HIGH, the output of invertor 105 is brought to a LOW level and the output enable terminal G1c of first three-status buffer G1 is brought to a LOW level. Hence, the output of first three-status buffer G1 is brought to a high-impedance state. In view of the low-level output of the invertor 105, no base current is supplied to PNP transistor Q1 through base resistor R1 and, PNP transistor Q1 is therefore maintained in an ON state. The output of non-inverting output terminal 103 is brought to a HIGH level.
When the logical level of the transmitted data supplied to data input terminal 102 is changed from a HIGH level to a LOW level, the output of invertor 105 is changed from a LOW level to a HIGH level and both output enable terminal G1c and input terminal G1a of first three-status buffer G1 are brought to a HIGH level. The output of first three-status buffer G1 is thus brought to a HIGH level. The base of PNP transistor Q1 is therefore brought to such a state that it is connected to the side of positive power source V+ by a low impedance through a high-level output transistor within first three-status buffer G1. Thus, it becomes possible to forcibly discharge the charge stored on the base of PNP transistor Q1 and shorten the cut-off delay time (turn off time).
With further regard to FIG. 6 and FIG. 7, when such a circuit configuration capable of short-circuiting the base and the emitter of a bipolar transistor by a low impedance is employed for shortening the turn off time of the bipolar transistor driving the output terminal, four signal lines are required to be placed between each output circuit and the logical circuit portion. Thus, the interface between the logical circuit portion and each output circuit becomes complicated. Furthermore, when it is attempted to fabricate the logical circuit portion as an IC, the number of output pins is undesirably increased.
When such a circuit configuration is employed in which a field effect transistor is used in place of the bipolar transistor driving the output terminal, the turn off time can be shortened by supplying through a low impedance a voltage to the gate of the field effect transistor for controlling the field effect transistor to be turned to an OFF state. However, there arises a problem similar to the above that the interface between the logical circuit portion and each output circuit becomes complicated.